A prototype-based SoC performance estimation methodology was proposed for consumer electronics design. Traditionally,\r\nprototypes are usually used in system verification before SoC tapeout, which is without accurate SoC performance exploration and\r\nestimation.This paper attempted to carefully model the SoC prototype as a performance estimator and explore the environment of\r\nSoC performance.The prototype met the gate-level cycle-accurate requirement, which covered the effect of embedded processor,\r\non-chip bus structure, IP design, embedded OS, GUI systems, and application programs.The prototype configuration, chip postlayout\r\nsimulation result, and the measured parameters of SoC prototypes were merged to model a target SoC design. The system\r\nperformance was examined according to the proposed estimation models, the profiling result of the application programs ported\r\non prototypes, and the timing parameters from the post-layout simulation of the target SoC. The experimental result showed that\r\nthe proposed method was accompanied with only an average of 2.08% of error for an MPEG-4 decoder SoC at simple profile level\r\n2 specifications.
Loading....